Plastic package decapsulation (or depacking) is absolutely necessary for construction analysis and failure analysis of plastic packaged components, typically semiconductor chips. Especially in the case of failure analysis, identification of the cause of a defective chip implies that the opening method keeps the full integrity of the devices integrated in the chip and of the metallic interconnections as well. Likewise, it is often necessary to physically evaluate VLSI devices for the purpose of product reliability, validation of physical design and identification of device structural patterns. Finally, at the present time, high volume supplies of verifiable bare chips are spotty in the merchant market since some suppliers will not even sell bare chips. This situation has forced some module manufacturers to purchase packaged chips and to remove the chips for re-use at considerably increased costs. Bare chip quality is the major issue of these module manufacturers, because they do not want to find themselves recovering chips not fully functional for re-use. As a result, in addition to functionality aspects, chip testability is also an essential concern, because the opening method must not only let the chip remain functional but also remain in good condition for the test. Therefore, the basic problem to be solved is to develop a reliable method to open plastic packaged modules to recover the bare semiconductor (typically silicon) chip enclosed therein without altering its physical and electrical integrity.
Wet chemical methods using hot fuming nitric acid are extensively used with silicon nitride (Si3N4) and/or silicon dioxide (SiO2) passivated silicon chips. When the silicon chip is passivated with polyimide, these methods are inoperative because nitric acid damages the polyimide material and thus does not preserve chip functionality (in case of polyimide passivation only manual polishing is used). A more specific problem has recently emerged with SiO2/Si3N4 passivated silicon chips, when very hard, etch resistant plastic resins are used as the molding compound to encapsulate the chip. For instance, the TOSHIBA "KE 2000H" plastic resin belongs to this category. This plastic resin has outstanding properties in terms of hermeticity, reliability, and purity (absence of contaminants). Unfortunately, the complete removal of this plastic resin without damaging the encapsulated chip is a very difficult task because the hard plastic resin is totally unattackable by any acid including hot fuming nitric acid.
FIG. 1 shows a conventional plastic packaged module of the SOJ (Small Outline J-Lead) model wherein a silicon chip is molded. FIG. 1 (A) shows a cutaway view of the plastic packaged module with a part of the plastic encapsulation removed, (B) shows a cross sectional view of the module, and (C) shows a schematic enlarged view at the vicinity of the chip terminal connection system. Now turning to FIG. 1 there is shown a conventional plastic packaged module 10 incorporating a silicon chip 11 whose active surface is mounted facing up. The packaged module 10 has a plurality of lead frame conductors 12 extending through the plastic encapsulating resin 13 which are adhesively joined to the silicon chip 11, preferably by means of a composite polymeric layer 14. Typically, this composite layer consists of a sandwich formed by a bottom polyimide polymeric layer 14a glued to an alpha barrier layer 14b. The alpha barrier layer is a film of a polymer material having a melting temperature above 175.degree. C. and does not contain ionizable species. One such polymer material that can be used as an alpha barrier is "KAPTON" (a trademark of DuPont). A 30 um diameter gold wire 15 is thermosonically bonded between each lead frame conductor 12 and a contact zone 19 of the chip. In addition, this composite polymeric layer 14 may reveal to be useful should the lead frame conductors dissipate excess heat that could damage the chip.
A more detailed construction at the vicinity of the terminal connection system where the gold wire 15 is attached to the chip 11 is shown in the enlarged view (C) of FIG. 1. Now turning to FIG. 1(C), there is illustrated a standard silicon chip 11 consisting of a silicon substrate 16 (wherein active/passive devices are formed) up to the phosphosilicate glass (PSG) insulating layer including the tungsten studs (not shown). The first metallization level (M1) is represented by land 17. A passivating layer 18 is formed thereon. Typically, according to the scope of the present invention, this passivating layer 18 is made of an inorganic material such as silicon nitride Si3N4 and/or silicon dioxide SiO2, as known by those skilled in the art. The passivation layer 18 is provided with an opening or via-hole. The second level of metallization (M2) is formed in this via-hole and results in a contact zone 19 where the gold wire 15 is bonded. For instance, according to an advanced CMOS technology used to manufacture 16 Mbits DRAM chips, the first and second metallization levels consist of a composite metallurgy: Ti-AlCuSi-TiN-Si and Ti-AlCuSi-TiN respectively. The other end of the gold wire 15 is bonded to one of the inner lead or lead frame conductor 12 (not shown). When the gold wire 15 is thermosonically bonded to the chip contact zone 19, there is formed a ball-shaped connection 20.
With continued reference to FIG. 1, the chip contact zones 19 are preferably located along a center area of the chip 11 along the longitudinal axis. As such, the plastic packaged module 10 of FIG. 1, is very attractive in many respects. In addition to its role of serving as an alpha barrier, the composite polymeric layer 14 cooperates lead frame conductors 12 (which cover a substantial portion of the chip surface) to facilitate the dissipation of heat generated by the chip. Moreover, the short connecting wires 15 contribute to faster chip response. This particular chip/packaging combined technology is described and claimed in commonly assigned U.S. Pat. Nos. 4,796,098 and 4,862,245. This technology is extensively used for the packaging of 1, 4 and 16 Mbits DRAM chips (in this latter case, the central area containing the chip contact zones is transverse instead of being longitudinal as illustrated in FIG. 1) and is currently designated under the brand name of A-wire (A stands for Area-window).